Multiple sized bump bonds

ABSTRACT

A semiconductor structure and methods for the creation of solder bumps configured to carry a signal and solder bumps configured for ground planes and/or mechanical connections as well as methods for increasing reliability of a chip package generally include formation of multiple sized bump bonds on under bump metallization patterns and/or pads of the same dimension. The signal carrying solder bumps are larger in terms of diameter and bump height than solder bumps configured for ground plane and/or mechanical connections.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

This invention was made with Government support under Contract No.H98230-13-D-0173 by the National Security Agency. The Government hascertain rights to this invention.

BACKGROUND

The present invention generally relates to fabrication methods and theresulting structures for semiconductor devices. More specifically, thepresent invention relates to the structure and formation of differentsized solder bumps for signal carrying and solder bumps for ground planeand/or mechanical connections.

Generally, semiconductor devices utilize metal die pads for receivingand supplying signals to and from other circuitry. The die pad isusually in a rectangular shape, wherein some of the metal layers areutilized for carrying signals between the die pads and other circuitryof the IC chip. The other die pads are used for mechanical connectionsand/or ground connections. One method of die assembly utilizes a solderbumped die that are flip chip assembled onto a workpiece. Flip chipinterconnections provide short electrical connecting paths as comparedto wire bonds, and therefore better electrical performance includingspeed. Conventional semiconductor dies for flip chip applicationstypically have a single bump size including a single bump height and asingle bump diameter that that are formed over die pads of a singlefixed size. Other semiconductor dies vary the bump size but alter theheight of the receiving pad to compensate for bump size variation.

SUMMARY

The present invention is generally directed to semiconductor devicestructures and methods for forming the semiconductor structures. In oneor more embodiments, semiconductor device includes a plurality of underbump metallization (UBM) layers overlying a pad, wherein each one of theUBMs have the same dimension. A first solder bump is disposed onselected ones of the UBM layers. A second solder bump is disposed on theother ones of the UBM layers, wherein the first solder bumps have afirst diameter (d1) and the second solder bumps have a second diameter(d2), wherein d1 is greater than d2, and wherein the first solder bumpsare configured to carry signals between chips and the second solderbumps are configured for mechanical connection and/or groundconnections.

In one or more other embodiments, a semiconductor device includes aplurality of under bump metallization (UBM) layers overlying a pad,wherein each one of the UBMs have the same dimension. A first solderbump is disposed on selected ones of the UBM layers. A second solderbump is disposed on the other ones of the UBM layers, wherein the firstsolder bumps have a bump height (bh1) and the second solder bumps have abump height (bh2), wherein bh1 is greater than bh2, and wherein thefirst solder bumps are configured to carry signals between chips and thesecond solder bumps are configured for mechanical connection and/orground connections.

In still one or more other embodiments, a semiconductor device includesone or more solder bumps configured for carrying a signal; and one ormore solder bumps configured for ground plane or mechanical connection,wherein the one or more solder bumps configured for carrying the signalhave a greater bump height than the one or more solder bumps configuredfor ground plane or mechanical connection.

In one or more embodiments, a method for the creation of solder bumpsconfigured to carry a signal and solder bumps configured for groundplanes and/or mechanical connections includes providing a semiconductorsubstrate, at least two similarly dimensioned contact pads having beenprovided over the substrate, a passivation layer deposited over saidsubstrate, the passivation layer having at least two openings thataligns with the least two similarly dimensioned contact pads, and anunder bump metallization layer over each one of the least two similarlydimensioned contact pads. A photoresist layer is deposited onto thesubstrate and contact holes aligned with at least a portion of the atleast two contact pads are formed, wherein the contact holes for thecreation of solder bumps configured to carry the signal have a greaterdiameter than the contact holes for the creation of solder bumpsconfigured for ground planes and/or mechanical connections. The contactholes are filled with a solder metal to form solder columns. Thephotoresist removed, and the solder columns reflowed to form the solderbumps configured to carry the signal and the solder bumps configured forground planes and/or mechanical connections, wherein the solder bumpsconfigured to carry the signal have a greater bump height than thesolder bumps configured for ground planes and/or mechanical connections.

In one or more embodiments, a method of increasing reliability of a chippackage includes forming a plurality of under bump metallization (UBM)patterns on a surface of a substrate, wherein each one of the UBMpatterns is of the same dimension. A photoresist layer overlying thesurface is deposited and contact holes formed in the photoresist layer,wherein the contact holes are aligned to the UBM pattern, wherein aselected portion of the contact holes have a first diameter and theother portion of the contact holes have a second diameter, and whereinthe first diameter is greater than the second diameter. The contactholes are filled with a solder metal by an injection molding solderingprocess to form solder columns. The photoresist removed, and the soldercolumns reflowed to form solder bumps configured to carry a signal fromthe solder metal filled contact holes having the first diameter andsolder bumps configured for ground planes and/or mechanical connectionsfrom the solder metal filled contact holes having the second diameter,wherein the solder bumps configured to carry the signal have a bumpheight greater than the solder bumps configured for ground planes and/ormechanical connections.

Additional features and advantages are realized through the techniquesof the present invention. Other embodiments and aspects of the inventionare described in detail herein and are considered a part of the claimedinvention. For a better understanding of the invention with advantagesand features, refer to the description and to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The specifics of the exclusive rights described herein are particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The foregoing and other features and advantages ofthe embodiments of the invention are apparent from the followingdetailed description taken in conjunction with the accompanying drawingsin which:

FIG. 1 is a sectional view depicting a semiconductor device after afabrication operation according to embodiments of the invention;

FIG. 2 is a sectional view depicting a semiconductor device after afabrication operation according to embodiments of the invention; and

FIG. 3 is a sectional view depicting a semiconductor device after afabrication operation according to embodiments of the invention.

DETAILED DESCRIPTION

Exemplary embodiments of the invention will now be discussed in furtherdetail with regard to semiconductor devices and methods of manufacturingthe same and, in particular, to structures including different sizedsolder bump bonds for improved reliability and methods of manufacture.As will be described in greater detail, the methods and resultingstructures are fabricated such that the bump bonds configured forcarrying signals are larger than the bump bonds configured formechanical connections and/or for ground connections, wherein thedifferent sized solder bumps are formed on die pads (and under bumpmetallization layers) of the same dimension.

Packaging of the ULSI chip is one of the most important steps in ULSImanufacturing, contributing significantly to the overall cost,performance and reliability of the packaged chip. As semiconductordevices reach higher levels of integration, packaging technologies suchas chip bonding have become critical. Packaging of the chip accounts fora considerable portion of the cost of producing the device and failureof the package leads to costly yield reduction.

Some chip bonding technologies utilize a solder bump attached to acontact pad (chip bonding pad) on the chip to make an electricalconnection from the chip devices to the package. For example, C4(Controlled-Collapse Chip Connection) is a means of connectingsemiconductor chips to substrates in electronic packages. C4 is aflip-chip technology in which the interconnections are small solderballs (bumps) on the chip surface. Since the solder balls forms an areaarray, C4 technology can achieve the highest density scheme known in theart for chip interconnections. The flip chip method has the advantage ofachieving the highest density of interconnection to the device with thelowest parasitic inductance.

Solder bumps can be formed by, for example, vapor deposition of soldermaterial over layers of under bump metallization (UBM) formed on thechip bonding pad. In another method, the layers of solder material canbe deposited by electrodeposition onto a seed layer material depositedover UBM layers formed on the chip bonding pad. In yet another method,solder bumps can be formed by a solder-paste screen printing methodusing a mask (stencil) to guide the placement of the solder-paste.Typically, after deposition of the solder materials, for example, inlayers or as a homogeneous mixture, the solder bump (ball) is formedafter removing a photoresist mask defining the solder material locationby heating the solder material to a melting point where according to areflow process a solder ball is formed with the aid of surface tension.

The solder bump bonds are generally used for signal carrying, mechanicalconnection, and ground plane connections. The various solder bump bondsare not symmetrical within a given packaging scheme with signal carryingbump bonds being much fewer in number than bump bonds configured forground planes and/or for mechanical connection. The signal carryingbumps can be used for eventual connection to room temperatureelectronics. Because of this, the impact of a failed groundplane/mechanical connection is less significant than the impact of afailed signal carrying bump bond. Failure of the ground/mechanicalconnection can be tolerated given the redundancies built into asemiconductor device but signal carrying bump bonds are much morecritical and failure can be catastrophic. If rework is also considered,any design that favors integrity of the bump bonds configured for signalcarrying, potentially at the cost of a somewhat reduced yield of thebump bonds configured for mechanical/ground connections, isadvantageous. The present invention provides semiconductor devices suchas flip chips and methods of fabricating the same with different solderbump geometries for signal carrying bump bonds relative to those solderbumps configured for ground plane and/or mechanical connections. As willbe described in greater detail below, the signal carrying solder bumpsare fabricated to be larger diameter and have a higher height than theground plane and/or mechanical solder bumps, wherein the different sizedbumps can be formed from the same dimensioned under bump metallizationlayers and die pads.

It is to be understood that the various layers and/or regions shown inthe accompanying drawings are not drawn to scale, and that one or morelayers and/or regions of a type commonly used in complementarymetal-oxide semiconductor (CMOS), fin field-effect transistor (FinFET),metal-oxide-semiconductor field-effect transistor (MOSFET), and/or othersemiconductor devices, may not be explicitly shown in a given drawing.This does not imply that the layers and/or regions not explicitly shownare omitted from the actual devices. In addition, certain elements maybe left out of particular views for the sake of clarity and/orsimplicity when explanations are not necessarily focused on the omittedelements. Moreover, the same or similar reference numbers usedthroughout the drawings are used to denote the same or similar features,elements, or structures, and thus, a detailed explanation of the same orsimilar features, elements, or structures will not be repeated for eachof the drawings.

The terms “wafer” and “substrate” are used interchangeably and are to beunderstood as including silicon-on-insulator (SOI) orsilicon-on-sapphire (SOS) technology, doped and undoped semiconductors,epitaxial layers of silicon supported by a base semiconductorfoundation, and other semiconductor structures. Furthermore, whenreference is made to a “wafer” or “substrate” in the followingdescription, previous process steps may have been utilized to formregions or junctions in the base semiconductor structure or foundation.

The term “under bump metal (UBM) “or” under bump metallization (UBM)” asused herein refers to structures that adhere well both to the underlyingpad and to the surrounding circuits passivation layer, hermeticallysealing the circuits from the environment. In some cases, a UBM canprovide a strong barrier to prevent the diffusion of other bump metalsinto the circuits. A top layer of a UBM must be readily wettable by thebump metals, for solder reflow. In one or more embodiments, a UBM usesmultiple different metal layers, such as an adhesion layer, a diffusionbarrier layer, a solderable layer, and an oxidation barrier layer. It isfurther possible that the UBM layers are compatible metals which incombination have low internal mechanical stresses.

Copper, gold and nickel are among the more popular materials used forfabricating the UBM due to their conductivity at room temperature andtheir ability to provide structural support to the corresponding solderbumps. However, the present invention is not limited to copper, gold andnickel as other metals can be used as can be desired for differentapplications. For example, superconducting metals can be used.

The semiconductor devices and methods for forming same in accordancewith embodiments of the present invention can be employed inapplications, hardware, and/or electronic systems. Suitable hardware andsystems for implementing embodiments of the invention can include, butare not limited to, personal computers, communication networks,electronic commerce systems, portable communications devices (e.g., celland smart phones), solid-state media storage devices, functionalcircuitry, etc. Systems and hardware incorporating the semiconductordevices are contemplated embodiments of the invention. Given theteachings of embodiments of the invention provided herein, one ofordinary skill in the art will be able to contemplate otherimplementations and applications of embodiments of the invention.

The embodiments of the present invention can be used in connection withsemiconductor devices that can require, for example, CMOSs, MOSFETs,and/or FinFETs. By way of non-limiting example, the semiconductordevices can include, but are not limited to CMOS, MOSFET, and FinFETdevices, and/or semiconductor devices that use CMOS, MOSFET, and/orFinFET technology.

The following definitions and abbreviations are to be used for theinterpretation of the claims and the specification. As used herein, theterms “comprises,” “comprising,” “includes,” “including,” “has,”“having,” “contains” or “containing,” or any other variation thereof,are intended to cover a non-exclusive inclusion. For example, acomposition, a mixture, process, method, article, or apparatus thatcomprises a list of elements is not necessarily limited to only thoseelements but can include other elements not expressly listed or inherentto such composition, mixture, process, method, article, or apparatus.

As used herein, the articles “a” and “an” preceding an element orcomponent are intended to be nonrestrictive regarding the number ofinstances (i.e. occurrences) of the element or component. Therefore, “a”or “an” should be read to include one or at least one, and the singularword form of the element or component also includes the plural unlessthe number is obviously meant to be singular. Thus, for example,reference to a problem-solving system including “a solder bump” includesa single solder bump, or two or more solder bumps. It should also benoted that the term “or” is generally employed in its sense including“and/or” unless the content clearly dictates otherwise.

As used herein, the terms “invention” or “present invention” arenon-limiting terms and not intended to refer to any single aspect of theparticular invention but encompass all possible aspects as described inthe specification and the claims.

As used herein, the term “about” modifying the quantity of aningredient, component, or reactant of the invention employed refers tovariation in the numerical quantity that can occur, for example, throughtypical measuring and liquid handling procedures used for makingconcentrates or solutions. Furthermore, variation can occur frominadvertent error in measuring procedures, differences in themanufacture, source, or purity of the ingredients employed to make thecompositions or carry out the methods, and the like. In one aspect, theterm “about” means within 10% of the reported numerical value. Inanother aspect, the term “about” means within 5% of the reportednumerical value. Yet, in another aspect, the term “about” means within10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

It will also be understood that when an element, such as a layer,region, or substrate is referred to as being “on” or “over” anotherelement, it can be directly on the other element or intervening elementscan also be present. In contrast, when an element is referred to asbeing “directly on” or “directly over” another element, there are nointervening elements present, and the element is in contact with anotherelement.

Embodiments of the present invention include providing a semiconductordevice having a plurality of under bump metallization (UBM) layers ondie pads. The plurality of UBM layers and the corresponding die pads areof the same dimensions, wherein the solder bumps are selected to havedifferent sizes depending on whether they are configured for signalcarrying or for ground plane and/or mechanical connection. The solderbumps configured for signal carrying connections have a larger diameterand a greater height than the solder bumps utilized for otherconnections such as for ground planes and mechanical connections. As aresult, improved reliability is realized in the semiconductor devicebecause there is greater areal contact provided by the larger solderbump size of the signal carrying solder bumps when bonded to anothersubstrate, e.g., die.

As will be described in greater detail, the solder bumps can be formedusing an injection molding soldering process, wherein the amount ofinjected solder metal into a contact hole formed within a photoresistlayer for defining the solder bumps is generally dependent on the areatherein. In the present invention, the contact hole dimensions withinthe photoresist layer utilized to form signal carrying solder bumps arelarger than the contact hole dimensions utilized to form other types ofsolder bumps, e.g., ground planes and/or mechanical connections. In oneor more embodiments, the contact hole dimensions to form signal carryingsolder bumps is greater than a perimeter defined by the underlying UBMand die pad whereas the contact hole dimensions utilized to form othertypes of solder bumps is less than the perimeter defined by theunderlying UBM and die pad. Subsequent reflow of solder afterphotoresist removal will result in different diameter and differentheight solder bumps based on the area provided by photoresist contacthole even though the underlying UBM and die pad are of the samedimensions for all types of solder bumps.

FIGS. 1-3 provide cross sectional views of an exemplary chip bonding padand associated UBM layers and solder bumps for chip bonding in flip chiptechnology, wherein selected ones of the solder bumps are configured forsignal carrying and the other ones are configured for other connectionssuch as for ground plane and mechanical connections.

Referring now to FIG. 1, the process of creating the solder bumps issubsequent to formation and patterning of under bump metallizationlayers 16 on chip bonding pads 12 formed on a substrate 10. Thesubstrate 10 can be an integrated circuit having a plurality of tracesand electrodes or vias. Any number of individual traces and otherconductive features can be formed on a top surface. Such features can belocalized or can extend the full length of the top surface. Discretecomponents such as multi-pin electrical connectors, integrated circuits,resistors, capacitors, stiffeners, etc. can also be incorporated intothe top surface or integrated circuit as can be desired for the variousapplications.

The chip bonding pads 12, for example copper (Cu) or aluminum (Al), canbe formed by vapor deposition on the surface of the substrate 10.Typically, after the chip bonding pad 10 is formed, a passivation layer14 of, for example, silicon dioxide (SiO₂) polyimide, benzocyclobutene(BCB), silicon nitride, or the like, is formed over the substratesurface excluding a portion overlying the chip bonding pad 10. Aplurality of under bump metallization (UBM) layers, e.g., 16 of fromabout 500 Angstroms to about 5000 Angstroms are then formed over thechip bonding pad 10 and patterned. The UBM layer 16 can be, for example,a layer of titanium (Ti). The UBM layers are formed over the chipbonding pad 10 to allow for better bonding and wetting of the soldermaterial and for protection of the chip bonding pad. As shown, each ofthe UBM layers as well as the bonding pads have the same circumferentialdimensions.

In the present invention, a photoresist layer 18 is deposited onto thesubstrate and photolithographically patterned and developed to formcontact holes 19 a, 19 b above the contact pad 12 to expose at least aportion of the UBM layer 16. The photolithography process can include,for example, introducing electromagnetic radiation such as ultravioletlight through an overlay mask to cure a photoresist material (notshown). Depending upon whether the resist is positive or negative,uncured portions of the resist are removed to form the first resistpattern including openings to expose portions of the conductive metallayer, which can then be etched to form openings within the conductivemetal layer, thereby exposing portions of the underlying layer. Thematerial defining photoresist can be any appropriate type of photoresistmaterials, which can partly depend upon the device patterns to be formedand the exposure method used. For example, material of photo-resistlayer can include a single exposure resist suitable for, for example,argon fluoride (ArF); a double exposure resist suitable for, forexample, thermal cure system; and/or an extreme ultraviolet (EUV) resistsuitable for, for example, an optical process. The thin layer of metaldefining the UBM layer can be deposited by evaporation, sputtering or byelectroplating.

For the signal carrying solder bumps, contact holes 19 a are patternedto provide a larger diameter than the contact holes 19 b patterned forsolder bumps configured for mechanical connections and/or for groundplanes as shown. A column of solder material 20 can either be depositedin layers, for example, a layer of lead (Pb) followed by a layer of tin(Sn), the solder material layers later being formed into a homogeneoussolder during reflow, or can be deposited as a homogeneous soldermaterial by for example vapor deposition or by electroplating onto aseed layer or by an injection molding soldering (IMS) process.

By way of example, the IMS process can be used to fill the contact holes19 with molten solder or solder alloys of any composition. It isaccomplished by using an IMS head where the solder is loaded and meltedfirst and then placed tightly against the photoresist surface and glidedacross the surface. A vacuum channel is provided ahead of the solderslot such that the contact holes are under vacuum. Molten solder thenruns quickly into the openings that are under vacuum and thereby fillingthe contact holes 19 with molten solder. Because of the difference indiameters of the contact holes, the volume of solder placed on the UBMpad during the IMS process will vary according to the area of thecontact hole.

Referring now to FIG. 2, after the substrate is cooled, the photoresistlayer 18 can be removed leaving the as-deposited solder. The photoresistlayer can be selectively removed by a wet etching or dry etchingprocess, e.g., an ashing process. As shown, solder column 20 a has alarger diameter than the solder column 20 b. Both solder columns havethe same height at this stage.

In FIG. 3, the solder columns 20 a, 20 b are then heated to reflow toform a solder bumps 22 a, 22 b having a spherical or hemispherical likeshape over the UBM layer 16, wherein after reflow the solder bumps 22 a,22 b are of different heights and diameters. The bump heights for thedifferent solder bumps are generally dependent on the area defined bythe contact holes, which in part is dependent on the size of theunderlying pad and generally ranges from about 10 to 300 microns formost applications, although greater or smaller heights can be used. Thesignal carrying solder bumps 22 a have a greater diameter (d₁) and abump height (bh₁) than the diameter (d₂) and bump height (bh₂) for theground plane and/or mechanical connection solder bumps 22 b. Anysuitable process that heats the solder causing it to melt, and thenallows the material to subsequently cool and harden can be used.Examples include but are not limited to a wave solder machine, aninfrared heater, a forced hot air conduction system, an oven, asoldering iron, and the like.

In one or more embodiments, the diameter (d1) of the first solder bumpis up to 20 percent larger than the diameter (d2) of the second solderbumps. In other embodiments, the diameter (d1) of the first solder bumpis up to 10 percent larger than the diameter (d2) of the second solderbumps; and in still other embodiments, the diameter (d1) of the firstsolder bump is up to 5 percent larger than the diameter (d2) of thesecond solder bumps.

In one or more embodiments, a differential between bump height (bh1) ofthe first solder bumps and the bump height (bh2) of the second solderbumps, after reflow, is greater than 20 percent to less than 5 percent.In other embodiments the differential can be determined by measuring thedistribution in sizes of a population of bumps which are intended to beidentical in size, and choosing the signal bumps to be one to twostandard deviations larger in diameter than the rest of the population.

Most solder metals are alloys, or combinations of pure elements ormaterials. Alloys have very different melting characteristics comparedto their pure metal forms. Most alloys do not have a single meltingtemperature or melting point; instead they have a melting range. Theupper and lower limits of this range are called the liquidus and solidustemperatures, respectively. The solder begins to melt at its solidustemperature and continues to melt until it reaches the liquidustemperature, where it is completely molten. The difference between thesolidus and liquidus temperatures is referred to as the gap. Some solderalloys have a large gap, whereas others have a small or virtuallynon-existent gap. With a large gap, the application of solder bumpsdirectly to the IMS column is feasible because the amount of reflow iseasily controlled. If a solder alloy with a small or non-existent gap isused, controlling the amount of reflow can be difficult. The presentinvention can accomplish the desired result with a wide variety ofsolder alloys.

Advantageously, the larger bump size of the signal carrying solder bumpsimproves reliability because of the larger areal contact provided by theincreased size. The improved reliability can be tuned by adjusting thetotal force applied during the bonding process to that required for thesmaller solder bumps for ground plane and/or mechanical connection. Thelarger bumps will experience a larger force and hence a largerdeformation leading to a larger are of contact and machining it morelikely than the large bump connection is made.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdescribed herein.

What is claimed is:
 1. A semiconductor device, comprising: a pluralityof under bump metallization (UBM) layers overlying a pad, wherein eachone of the UBMs have the same dimension; a first solder bump on selectedones of the UBM layers; and a second solder bump on the other ones ofthe UBM layers, wherein the first solder bumps have a first diameter(d1) and the second solder bumps have a second diameter (d2), wherein d1is greater than d2, and wherein the first solder bumps are configured tocarry signals between chips and the second solder bumps are configuredfor mechanical connection and/or ground connections.
 2. Thesemiconductor device of claim 1, further comprising a passivation layerintermediate at least a portion of the pad and the UBM layer.
 3. Thesemiconductor device of claim 1, wherein the diameter (d1) of the firstsolder bump is up to 20 percent larger than the diameter (d2) of thesecond solder bumps.
 4. The semiconductor device of claim 1, wherein thediameter (d1) of the first solder bump is 1 to 2 standard deviationslarger than the diameter (d2) of the second solder bumps.
 5. Asemiconductor device, comprising: a plurality of under bumpmetallization (UBM) layers overlying a pad, wherein each one of the UBMshave the same dimension; a first solder bump on selected ones of the UBMlayers; and a second solder bump on the other ones of the UBM layers,wherein the first solder bumps have a bump height (bh1) and the secondsolder bumps have a bump height (bh2), wherein bh1 is greater than bh2,and wherein the first solder bumps are configured to carry signalsbetween chips and the second solder bumps are configured for mechanicalconnection and/or ground connections.
 6. The semiconductor device ofclaim 5, wherein bh2 is greater than 20 percent to less than 5 percentof bh2.
 7. The semiconductor device of claim 5, further comprising apassivation layer intermediate at least a portion of the pad and the UBMlayer.
 8. The semiconductor device of claim 5, wherein the diameter (d1)of the first solder bump is up to 20 percent larger than the diameter(d2) of the second solder bumps.
 9. The semiconductor device of claim 5,wherein the diameter (d1) of the first solder bump is 1 to 2 standarddeviations larger than the diameter (d2) of the second solder bumps.10-23. (canceled)
 24. A semiconductor device, comprising: one or moresolder bumps configured for carrying a signal; and one or more solderbumps configured for ground plane or mechanical connection, wherein theone or more solder bumps configured for carrying the signal have agreater bump height than the one or more solder bumps configured forground plane or mechanical connection.
 25. The semiconductor device ofclaim 24, wherein one or more solder bumps configured for carrying asignal and one or more solder bumps configured for ground plane ormechanical connection are formed on an under bump metallization pattern,wherein each under bump metallization pattern has the same dimensions.